دانلود رایگان مقاله لاتین طراحی قدرت کارآمد sram از سایت الزویر
عنوان فارسی مقاله:
طراحی قدرت کارآمد SRAM با لاین پمپ شارژ یکپارچه
عنوان انگلیسی مقاله:
Power efficient SRAM design with integrated bit line charge pump
سال انتشار : 2016
برای دانلود رایگان مقاله طراحی قدرت کارآمد sram اینجا کلیک نمایید.
مقدمه انگلیسی مقاله:
1. Introduction
In the past few decades, CMOS technology has been scaling down by Moore’s law. Transistor channel length has been decreasing by the use of advanced manufacturing process. With the tremendous boost of integrated circuit performance, interconnection metals become more and more complex. Signal switching in these interconnection lines results in significant power consumption as well as heat generation. These drawbacks become more severe in memory systems, where interconnection metals dominate power dissipation of the entire block. For example, the charging and discharging activity of bit lines is the primary cause in SRAM, since they are long routing metals and connect to a large column of memory cells. Power in SRAM is mainly consumed by bit line charge and discharge currents. Therefore, in order to lower the power consumption of SRAM, suppressing bit line swing is substantially important [1]. The first charge pump was proposed by Dickson [2]. Later, a variety of optimized charge pumps were presented in literature [3–7]. The principle of charge pump is using two clock signals to modify connection states of capacitors. In most cases, charge pump provides a stable voltage supply other than power supply. So they are widely used as dc-dc converting circuits in power management systems [8]. The contribution of this work is that we integrate a charge pump circuit with SRAM and realize an efficient charge recycling SRAM system. The whole memory system was designed and implemented in 180 nm CMOS process. The post-layout simulation shows an 11% of power reduction and only 3.8% of area overhead due to the integration of bit line charge pump when a SRAM has 8 bits. If the bit width of SRAM increases to 64, the resultant power saving is about 22%. Furthermore, this SRAM layout was embedded into an 8051 MCU layout to verify its operation compatibility. Simulation results demonstrate the 8051 MCU system works correctly with the proposed charge pump SRAM. The remainder of this paper is organized as follows. Section 2 presents a review of the related works on low power SRAM system design. In Section 3, we present the proposed charge pump design scheme. In Section 4, we present the simulation results including operational timing chart, power consumption analysis, efficiency calculation and PVT simulation. In Section 5, we provide the validation and benefits of our proposed SRAM scheme for energyefficient operation, while Section 6 concludes the paper.
برای دانلود رایگان مقاله طراحی قدرت کارآمد sram اینجا کلیک نمایید.
کلمات کلیدی:
Power Efficient SRAM Cell and Array Design | SPORT Lab sportlab.usc.edu/presentations/power-efficient-sram-cell-and-array-design/ Power Efficient SRAM Cell and Array Design. Low-Leakage SRAM Design in Deep Submicron Technologies — This January-2008 presentation has two parts. [PDF]A Power-Efficient SRAM Core Architecture with Segmentation ... - CS28 www28.cs.kobe-u.ac.jp/~kawapy/publications/VLSIDAT08RECTSRAM.pdf by Y Murachi - Cited by 9 - Related articles A Power-Efficient SRAM Core Architecture with Segmentation-Free and. Rectangular Accessibility for Super-Parallel Video Processing. Yuichiro Murachi ... A comparative study of power efficient SRAM designs dl.acm.org/citation.cfm?id=331018 by J Hezavei - 2000 - Cited by 14 - Related articles Mar 2, 2000 - This paper investigates the effectiveness of combination of different low power SRAM circuit design techniques. The divided bit line (DBL), ... A Comparative Study of Power Efficient SRAM ... - ACM Digital Library dl.acm.org/ft_gateway.cfm?ftid=3245&id=331018 by J Hezavei - 2000 - Cited by 14 - Related articles A Comparative Study of Power Efficient SRAM Designs. Jeyran Hezavei, N. Vijaykrishnan, M. J. Irwin. 220 Pond Lab,. Department of Computer Science ... [PDF]Power efficient SRAM design with integrated bit line charge pump iranarze.ir/wp-content/uploads/2016/10/E2061.pdf Power efficient SRAM design with integrated bit line charge pump. Xu Wang a,b,*. , Yuanzhi Zhang c, Chao Lu c, Zhigang Mao a a Department of Micro-Nano ... [PDF]energy efficient sram - IIIT Hyderabad web2py.iiit.ac.in/.../phdthesis.pdf.b1b95363d9b1e33d.532e204d616d617468612028... This Thesis proposes energy efficient SRAM cells (6T and 5T) based on adiabatic principles and design modifications. Bulk of the energy in SRAMs is wasted ... The Design and Implementation of a Power Efficient Embedded SRAM ... link.springer.com/chapter/10.1007/978-3-540-74442-9_9 by Y Liu - 2007 - Related articles Abstract. In this paper, a power efficient 2K asynchronous SRAM is presented for embedded applications. The SRAM adopts a low swing write scheme, which ...
