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عنوان انگلیسی مقاله:

High-speed low-power comparator for analog to digital converters


سال انتشار : 2016



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مقدمه انگلیسی مقاله:

1. Introduction

Low-power high-speed ADCs are natural candidates for portable electronic devices [1–19]. Comparators play an important role in efficiency of commonly used ADCs, such as Flash and SAR ADCs [5–8,16–19]. Static comparators have been used in the past, however, they are impractical for portable applications because of their limited speed and significant amounts of power consumption [1]. One-stage dynamic comparators were proposed to reduce the power consumption and improve the speed [2]. These comparators, however, suffer from an inherent trade-off between the power consumption and offset voltage [3]. Moreover, one-stage dynamic comparators suffer from kick-back noise caused through the capacitive path from the output nodes to the input nodes of the comparator [3]. Two-stage dynamic comparators were proposed to mitigate the kickback noise and decouple the offset versus speed trade-off of the single-stage dynamic comparators [4]. In the two-stage dynamic comparators, the input transistors are chosen large enough to achieve a given offset voltage. In fact, the overall offset of the comparator is almost dominated by the first stage [1]. Using large transistors at the input leads to large parasitic capacitors at the output of the first stage of the comparator. Consequently, there is an inherent trade-off between power consumption and offset voltage. Recently some methods are reported to enhance the speed and reduce power consumption, or offset voltage. These methods have their own advantages and disadvantages which are briefly described as follows. In [5], a two stage comparator is presented working with only one clock phase to reduce the complexity and power consumption. In this comparator, a time domain bulk tuned offset cancelation is used to achieve a low offset voltage. With lower offset voltage smaller transistors can be employed resulting in a lower power consumption. However, this offset cancelation method limits the speed significantly. In [6], another structure for a two-stage comparator is presented which achieves a higher speed at the expense of higher power consumption. The circuit of [7] presents a highspeed input common mode voltage ðVcmÞ insensitive comparator. In this comparator, there is a capacitive path from the output to the input which leads to a large kickback noise. The comparator of [8] uses a delayed clock signal to reduce power consumption and enhance the speed. In this circuit, the delayed clock signal helps increasing the preamplifier gain and reducing the delay of the latch circuit, however, this circuit suffers from kickback noise. Since the latch and preamplifier stages are coupled together, this circuit is not a good choice for high precision applications. In fact, the large sizing of both preamplifier and latch stages (to achieve a low offset voltage) results in a higher power consumption. In the proposed comparator, the voltage variation of the first stage is minimized to achieve a high-speed low-power comparator with an acceptable offset voltage. Moreover, the proposed circuit improves the input common mode range, as the latch stage is activated stronger than the conventional circuit. Analytical derivations are presented which verify the benefits of the proposed comparator and predict its delay precisely. Section 2 presents the circuit of the conventional and proposed comparator. In Section 3, analytical derivations are discussed. In Section 4, Vcm generation is discussed. Section 5 presents the schematic and post layout simulation results. Section 6 concludes the paper.



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